Decaps are physical only cells that are added for PG stability. The proper PG distribution is important due to these reasons:
1) The IR drop is critical in the PG network. Abnormal IR drops can lead to the cells getting powered up/ switched off at non-desired intervals. This migh impact the functionality. Also, a delay in switching of the cells can lead to timing issues. Just to recollect, the amount o voltage applied to the drain of the MOS transitor is proportional to the amount of current that flows through the MOS transistor.
2) Reliability: Hot spots in the chip might result from excessive voltage drops. These are observed mostly near the clock rows/clock paths and the PG network.
The IR drops in the PG network are maintained minimal by routing the PG nets in higher metal layers as they have lesser resistance, through advanced PG grid structures (like alternating between VDD and VSS nets for every double repeatition etc), having more VDD and VSS pins for the standard cells etc.
To stabilize the PG network and act against the effects of inductance in the network leading to IR drops (R+Ldi/dt), the decaps are used.
The decaps are placed all over the design. They store the charge and provide the power for switching. The power and ground bounce does not impact the cells as it can't be bypassed by decaps.
To decide on the numbers that are ideally needed for a given design, first the voltage supply magnitude swing and noise budgets need to be finalized. For a 10% noise budget, Cdecap=9Cload.
So, roughly for a 100k gate count (relative to NAND gate), we need 900k decaps assuming loaded functionality.
1) The IR drop is critical in the PG network. Abnormal IR drops can lead to the cells getting powered up/ switched off at non-desired intervals. This migh impact the functionality. Also, a delay in switching of the cells can lead to timing issues. Just to recollect, the amount o voltage applied to the drain of the MOS transitor is proportional to the amount of current that flows through the MOS transistor.
2) Reliability: Hot spots in the chip might result from excessive voltage drops. These are observed mostly near the clock rows/clock paths and the PG network.
The IR drops in the PG network are maintained minimal by routing the PG nets in higher metal layers as they have lesser resistance, through advanced PG grid structures (like alternating between VDD and VSS nets for every double repeatition etc), having more VDD and VSS pins for the standard cells etc.
To stabilize the PG network and act against the effects of inductance in the network leading to IR drops (R+Ldi/dt), the decaps are used.
The decaps are placed all over the design. They store the charge and provide the power for switching. The power and ground bounce does not impact the cells as it can't be bypassed by decaps.
To decide on the numbers that are ideally needed for a given design, first the voltage supply magnitude swing and noise budgets need to be finalized. For a 10% noise budget, Cdecap=9Cload.
So, roughly for a 100k gate count (relative to NAND gate), we need 900k decaps assuming loaded functionality.
