Decaps

Decaps are physical only cells that are added for PG stability. The proper PG distribution is important due to these reasons:
1) The IR drop is critical in the PG network. Abnormal IR drops can lead to the cells getting powered up/ switched off at non-desired intervals. This migh impact the functionality. Also, a delay in switching of the cells can lead to timing issues. Just to recollect, the amount o voltage applied to the drain of the MOS transitor is proportional to the amount of current that flows through the MOS transistor.
2) Reliability: Hot spots in the chip might result from excessive voltage drops. These are observed mostly near the clock rows/clock paths and the PG network.

The IR drops in the PG network are maintained minimal by routing the PG nets in higher metal layers as they have lesser resistance, through advanced PG grid structures (like alternating between VDD and VSS nets for every double repeatition etc), having more VDD and VSS pins for the standard cells etc.

To stabilize the PG network and act against the effects of inductance in the network leading to IR drops (R+Ldi/dt), the decaps are used. 

The decaps are placed all over the design. They store the charge and provide the power for switching. The power and ground bounce does not impact the cells as it can't be bypassed by decaps.



To decide on the numbers that are ideally needed for a given design, first the voltage supply magnitude swing and noise budgets need to be finalized. For a 10% noise budget, Cdecap=9Cload.
So, roughly for a 100k gate count (relative to NAND gate), we need 900k decaps assuming loaded functionality.

PLL overview

 

The PLL(phase locked loop) is often the most important analog component

used in SoCs and other clocked circuits. What might wonder us when somebody

says that his/her device works fast is how fast that can be or whether

the claim is relative? The answer lies in the performance of this entity, the PLL.

The design and the verification of the specs is indeed the biggest

challenge. The performance of the PLL is critical because it generates the

clocking signal required to sequence the execution of the entire chip.

I would like to present  summary of the working and the composite of

the same in this section.

The PLL works like a closed-loop control system.

It comprises of the phase detector (which in the simplest case can be an

XOR gate. The phases of the input signal and the feedback signal are

compared), the loop filter (this is normally a lowpass filter) and the Voltage Controlled

oscillator (VCO can in the simplest way be implemented from the Wein Bridge

Oscillator that amplifies the voltage and produces an output

that is dependent on the feedback factor- determined by the 2 resistors).

If the output frequency is to be the same as that of the input, then

there is no need of any frequency divider to be placed at the feedback

path, else a divider can be used that divides the frequency in suitable steps.

The input signal can be that from any oscillator such as Quartz.

The design is critical in terms of the choice of the feedback resistors,

the loop filter.