PLL overview

 

The PLL(phase locked loop) is often the most important analog component

used in SoCs and other clocked circuits. What might wonder us when somebody

says that his/her device works fast is how fast that can be or whether

the claim is relative? The answer lies in the performance of this entity, the PLL.

The design and the verification of the specs is indeed the biggest

challenge. The performance of the PLL is critical because it generates the

clocking signal required to sequence the execution of the entire chip.

I would like to present  summary of the working and the composite of

the same in this section.

The PLL works like a closed-loop control system.

It comprises of the phase detector (which in the simplest case can be an

XOR gate. The phases of the input signal and the feedback signal are

compared), the loop filter (this is normally a lowpass filter) and the Voltage Controlled

oscillator (VCO can in the simplest way be implemented from the Wein Bridge

Oscillator that amplifies the voltage and produces an output

that is dependent on the feedback factor- determined by the 2 resistors).

If the output frequency is to be the same as that of the input, then

there is no need of any frequency divider to be placed at the feedback

path, else a divider can be used that divides the frequency in suitable steps.

The input signal can be that from any oscillator such as Quartz.

The design is critical in terms of the choice of the feedback resistors,

the loop filter.