Solving hold time violations

In most scenarios, the winner in hold failure resolution is the increase of the datapath delay without affecting the setup time. If this is not possible, then the negative skew component is increased/positive skew component is reduced keeping in mind the setup timing. But, this is not normally practiced.

Also, note that unlike the setup time resolution, the hold failures have nothing to do with the RTL and hence the resolution has to happen at the PD stage of the design.

Increasing the datapath delay:

1)      This is achieved through addition of buffers at the timing arcs of cells which are part of the timing paths that are failing hold but not setup. Normally, the designer would query the setup timing on each of the input pins of cells (not just the timing arcs that are part of the failing hold timing path) and if enough slack is seen, then the hold buffers can be added at these points. The exact number of hold buffers added depends on the quantum of the failure. The library team would give the appropriate buffer sizes and buffers characterized to ensure that the delay for these cells does not cause damage at the slow corners.

2)      For marginal hold failures that don’t need a buffer/cell addition, then detours through a routing tool like the one supported by ICC can be used. But, the designer needs to be cautious of the si components acting on the nets as at times, detours can have a positive secondary crosstalk effect, hence making the signal transition faster. This will reduce the net delay hence worsening hold. So, for si hold violations, the best fix in route detours is to have the aggressor information. For ba hold violations, route detours adds delay and fixes the hold violation.

3)      Managing the AOCV derate values: The derate values applied should have gone through lot of experimentation. The derates applied may be too optimistic leading to hold violations. The derates should ideally be PVT corner dependent.

4)      Cell swaps: If the cells in the path are not failing setup timing, then the cells can be swapped to hvt. The hvt cells have inherent low drive capability and so offer more delay.

Clock skewing:

This is not suggested as the CTS will be built keeping the setup timing in mind. But, if there is enough slack on the launch side of the path, then additional CTS inverters can be added, hence inducing negative skew and fixing hold.