LSSD vs MUXD cell. Which is better?

The scan cells as part of the DFT stitching process that are normally used are the MUX-D cell and the
LSSD cell. In newer technologies (45nm and lesser); the Mux D cell is not used because of the the combinational elements and
the inherent impact on the controllability thats a major concern in semmiconductor testing.

The LSSD cell, though offers a lesser usable slack is inherently a master-slave flop flop/ latch combination and is free from the effects of
combinational logic- hence better controllability and observability. Even in terms of area and power; LSSD cell fairs better.

In making the choice of which is better; it just depends on the technology. MUX-D is better if we can offer just one scan clock. No phase relationships to be maintained if the select signal is strobed. But, with MUX (again a combinational logic), there can be guaranteed uncertainty.

The LSSD cell needs the proper non-overlapping phase relationship to be maintained between the scan clocks and the free running clock and between themselves; and of course the timing overhead. Apart from that, in terms of performance, this will be a better choice.

//muxdcell.v
//`include "userprocs.v"
module muxdcell (d,scan_d,clk,sel,q);
input d,clk,sel,scan_d;
output q;
reg q;
wire a1,a2,a3,data;
assign a3=~sel;
assign a1=sel&scan_d; //sel enables the operation in scan mode
assign a2=d&a3;
assign data=a1|a2;//delay may be added to compensate the combinational overhead
always@(posedge clk)
begin
q<=data;
end
endmodule

//lssd cell.v
module lssd(clk,q,scan_in,scan_1,scan_cntrl,scan_2,latch_output,d);
input clk,scan_1,scan_2,scan_cntrl,d,scan_in;
output reg q,latch_output;
wire a;
wire b;

assign b=latch_output;
assign a=scan_cntrl&1'b1;
always@(clk or a or scan_1)//the master is controlled by the transition on scan_cntrl
begin
if(scan_1==1'b0)
latch_output<=d;
else
latch_output<=scan_in;//assuming that the scan and free running clocks are synchronous and have a definite phase relationship
end

always@(posedge clk)
begin
q<=d;
end

always@(scan_2 or a)
begin
q<=b;
end

Overview of ASIC domain partitioning

The power, area and timing metrics are often competitive in character. But, when partitioning the IC in terms of logic is facilitating in terms of the ASIC flow (like synthesis, placement and full chip build); but when it comes to the chiplet and integration, the partitioning rules are in terms of clock, power domains that are included at the specs level itself.

Clock happens to be the net that has the highest fanout in the design and and since its always ON, it consumes the maximum power. To reduce the frequency proves costly and so its better to cut off logic that are either in the sleep / standby states. To do this, what is often followed is clock gating where in the control logic (defined by the change of states at the architecture level of any design or an FSM meant for it) gates the clock to a particular block. This is the most effective way to reduce power at a less area and timing overhead. There are different styles of gating that are implemented. The simplest being the ANDing of the control signal and the free running clock leading to unpredictable glitches in the gated clock; and the latch based gating to pass the clock in the window defined by the latch. Both, are used depending on the design requisites.

The other partitioning strategy is in terms of power, where depending on the requirements of a design like a SOC embedded in a cellphone, the core is partitioned in terms voltage/ thus the power domains. Let us say, there's a core unit reading in data from the memory and if the data access is happening independent of the transaction with the display; then its better that the display be in the standby mode. Here, the clock gating cannot be effective as we are still not through with the inherent leakage and other static effects. Hence, its better to turn off the logic at the transistor level. The methodologies used are often at the transistor level and the choice of selection of a particular cell (power gated vs the ungated) lies with the designer.

A simple, yet effective strategy is to use sleep transistors; or the header or the footer cells. The gating control for these cells have to be defined at the architectural level. The leakage effects are considerably reduced, but with an area overhead. Also di/dt effects will be impinging more on the new power domains.