The power, area and timing metrics are often competitive in character. But, when partitioning the IC in terms of logic is facilitating in terms of the ASIC flow (like synthesis, placement and full chip build); but when it comes to the chiplet and integration, the partitioning rules are in terms of clock, power domains that are included at the specs level itself.
Clock happens to be the net that has the highest fanout in the design and and since its always ON, it consumes the maximum power. To reduce the frequency proves costly and so its better to cut off logic that are either in the sleep / standby states. To do this, what is often followed is clock gating where in the control logic (defined by the change of states at the architecture level of any design or an FSM meant for it) gates the clock to a particular block. This is the most effective way to reduce power at a less area and timing overhead. There are different styles of gating that are implemented. The simplest being the ANDing of the control signal and the free running clock leading to unpredictable glitches in the gated clock; and the latch based gating to pass the clock in the window defined by the latch. Both, are used depending on the design requisites.
The other partitioning strategy is in terms of power, where depending on the requirements of a design like a SOC embedded in a cellphone, the core is partitioned in terms voltage/ thus the power domains. Let us say, there's a core unit reading in data from the memory and if the data access is happening independent of the transaction with the display; then its better that the display be in the standby mode. Here, the clock gating cannot be effective as we are still not through with the inherent leakage and other static effects. Hence, its better to turn off the logic at the transistor level. The methodologies used are often at the transistor level and the choice of selection of a particular cell (power gated vs the ungated) lies with the designer.
A simple, yet effective strategy is to use sleep transistors; or the header or the footer cells. The gating control for these cells have to be defined at the architectural level. The leakage effects are considerably reduced, but with an area overhead. Also di/dt effects will be impinging more on the new power domains.
Clock happens to be the net that has the highest fanout in the design and and since its always ON, it consumes the maximum power. To reduce the frequency proves costly and so its better to cut off logic that are either in the sleep / standby states. To do this, what is often followed is clock gating where in the control logic (defined by the change of states at the architecture level of any design or an FSM meant for it) gates the clock to a particular block. This is the most effective way to reduce power at a less area and timing overhead. There are different styles of gating that are implemented. The simplest being the ANDing of the control signal and the free running clock leading to unpredictable glitches in the gated clock; and the latch based gating to pass the clock in the window defined by the latch. Both, are used depending on the design requisites.
The other partitioning strategy is in terms of power, where depending on the requirements of a design like a SOC embedded in a cellphone, the core is partitioned in terms voltage/ thus the power domains. Let us say, there's a core unit reading in data from the memory and if the data access is happening independent of the transaction with the display; then its better that the display be in the standby mode. Here, the clock gating cannot be effective as we are still not through with the inherent leakage and other static effects. Hence, its better to turn off the logic at the transistor level. The methodologies used are often at the transistor level and the choice of selection of a particular cell (power gated vs the ungated) lies with the designer.
A simple, yet effective strategy is to use sleep transistors; or the header or the footer cells. The gating control for these cells have to be defined at the architectural level. The leakage effects are considerably reduced, but with an area overhead. Also di/dt effects will be impinging more on the new power domains.
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