The scan cells as part of the DFT stitching process that are normally used are the MUX-D cell and the
LSSD cell. In newer technologies (45nm and lesser); the Mux D cell is not used because of the the combinational elements and
the inherent impact on the controllability thats a major concern in semmiconductor testing.
The LSSD cell, though offers a lesser usable slack is inherently a master-slave flop flop/ latch combination and is free from the effects of
combinational logic- hence better controllability and observability. Even in terms of area and power; LSSD cell fairs better.
In making the choice of which is better; it just depends on the technology. MUX-D is better if we can offer just one scan clock. No phase relationships to be maintained if the select signal is strobed. But, with MUX (again a combinational logic), there can be guaranteed uncertainty.
The LSSD cell needs the proper non-overlapping phase relationship to be maintained between the scan clocks and the free running clock and between themselves; and of course the timing overhead. Apart from that, in terms of performance, this will be a better choice.
//muxdcell.v
//`include "userprocs.v"
module muxdcell (d,scan_d,clk,sel,q);
input d,clk,sel,scan_d;
output q;
reg q;
wire a1,a2,a3,data;
assign a3=~sel;
assign a1=sel&scan_d; //sel enables the operation in scan mode
assign a2=d&a3;
assign data=a1|a2;//delay may be added to compensate the combinational overhead
always@(posedge clk)
begin
q<=data;
end
endmodule
//lssd cell.v
module lssd(clk,q,scan_in,scan_1,scan_cntrl,scan_2,latch_output,d);
input clk,scan_1,scan_2,scan_cntrl,d,scan_in;
output reg q,latch_output;
wire a;
wire b;
assign b=latch_output;
assign a=scan_cntrl&1'b1;
always@(clk or a or scan_1)//the master is controlled by the transition on scan_cntrl
begin
if(scan_1==1'b0)
latch_output<=d;
else
latch_output<=scan_in;//assuming that the scan and free running clocks are synchronous and have a definite phase relationship
end
always@(posedge clk)
begin
q<=d;
end
always@(scan_2 or a)
begin
q<=b;
end
LSSD cell. In newer technologies (45nm and lesser); the Mux D cell is not used because of the the combinational elements and
the inherent impact on the controllability thats a major concern in semmiconductor testing.
The LSSD cell, though offers a lesser usable slack is inherently a master-slave flop flop/ latch combination and is free from the effects of
combinational logic- hence better controllability and observability. Even in terms of area and power; LSSD cell fairs better.
In making the choice of which is better; it just depends on the technology. MUX-D is better if we can offer just one scan clock. No phase relationships to be maintained if the select signal is strobed. But, with MUX (again a combinational logic), there can be guaranteed uncertainty.
The LSSD cell needs the proper non-overlapping phase relationship to be maintained between the scan clocks and the free running clock and between themselves; and of course the timing overhead. Apart from that, in terms of performance, this will be a better choice.
//muxdcell.v
//`include "userprocs.v"
module muxdcell (d,scan_d,clk,sel,q);
input d,clk,sel,scan_d;
output q;
reg q;
wire a1,a2,a3,data;
assign a3=~sel;
assign a1=sel&scan_d; //sel enables the operation in scan mode
assign a2=d&a3;
assign data=a1|a2;//delay may be added to compensate the combinational overhead
always@(posedge clk)
begin
q<=data;
end
endmodule
//lssd cell.v
module lssd(clk,q,scan_in,scan_1,scan_cntrl,scan_2,latch_output,d);
input clk,scan_1,scan_2,scan_cntrl,d,scan_in;
output reg q,latch_output;
wire a;
wire b;
assign b=latch_output;
assign a=scan_cntrl&1'b1;
always@(clk or a or scan_1)//the master is controlled by the transition on scan_cntrl
begin
if(scan_1==1'b0)
latch_output<=d;
else
latch_output<=scan_in;//assuming that the scan and free running clocks are synchronous and have a definite phase relationship
end
always@(posedge clk)
begin
q<=d;
end
always@(scan_2 or a)
begin
q<=b;
end


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